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A fast and accurate approach for common path pessimism removal in static timing analysis

Published in 2016 IEEE International Symposium on Circuits and Systems (ISCAS), 2016

The dual-mode delay model, while being effective for characterizing on-chip timing variations, also yields timing analysis results that are overly pessimistic due to the Common Path Pessimism (CPP). In this paper, we develop a fast and accurate block-based algorithm for removing this pessimism in timing analysis, when the dual-mode delay model is used. We illustrate the effectiveness of our algorithm on a set of benchmarks from the TAU 2014 Contest.

Recommended citation: Your Name, You. (2009). "Paper Title Number 1." Journal 1. 1(1).